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CS5451
Six-Channel Delta-Sigma Analog-to-Digital Converter
Features
l Synchronous
Description
The CS5451 is a highly integrated Delta-Sigma () Analog-to-Digital Converter (ADC) developed for the Power Measurement Industry. The CS5451 combines six ADCs, decimation filters, and a serial interface on a single chip. The CS5451 interfaces directly to a current transformer or shunt to measure current, and resistive divider or transformer to measure voltage. The product features a serial interface for communication with a micro-controller or DSP. The product is initialized and fully functional upon reset, and includes a Voltage Reference.
Sampling l On-chip 1.2 V Reference (25 ppm/C typ) l Power Supply Configurations:
- VA+ = +3 V; VA- = -2 V; VD+ = +3 V - Supply tolerances 10%
l Power l Simple
Consumption
- 20 mW Typical at VD+ = +3 V
Four-wire Serial Interface l Charge Pump Driver output generates negative power supply. l Ground-Referenced Bipolar Inputs
ORDERING INFORMATION: CS5451-BS -40C to +85C 28-pin SSOP
VA+ GAIN IIN1+ IIN1VIN1+ VIN14th Order Modulator
RESET
VD+
x1, 20
Decimation Filter
x1
2nd Order Modulator
Decimation Filter
IIN2+ IIN2VIN2+ VIN2-
x1, 20
4th Order Modulator
Decimation Filter
SE
x1
2nd Order Modulator 4th Order Modulator
Decimation Filter Serial Interface
OWRS SDO FSO
SCLK
IIN3+ IIN3VIN3+ VIN3VREFIN VREFOUT
x1, 20
Decimation Filter
x1
2nd Order Modulator
Decimation Filter
x1
Voltage Reference
CLOCK
Pulse Output Regulator
CPD
AGND
VA-
XIN
DGND
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2000 (All Rights Reserved)
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TABLE OF CONTENTS
1. CHARACTERISTICS AND SPECIFICATIONS ........................................................................ 3 ANALOG CHARACTERISTICS ................................................................................................ 3 ANALOG CHARACTERISITCS ................................................................................................ 4 DIGITAL CHARACTERISTICS ................................................................................................. 4 RECOMMENDED OPERATING CONDITIONS ....................................................................... 5 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 5 SWITCHING CHARACTERISTICS .......................................................................................... 6 2. GENERAL DESCRIPTION ....................................................................................................... 7 2.1 Theory of Operation ........................................................................................................... 7 2.2 Performing Measurements ................................................................................................. 8 2.3 High Rate Digital Filters ..................................................................................................... 8 2.4 Serial Interface ................................................................................................................... 8 2.5 System Initialization ........................................................................................................... 9 2.6 Analog Inputs ..................................................................................................................... 9 2.7 Voltage Reference ............................................................................................................. 9 2.8 Power Supply ..................................................................................................................... 9 2.9 PCB Layout ...................................................................................................................... 10 3. PIN DESCRIPTION ................................................................................................................. 11 4. PACKAGE DIMENSIONS........................................................................................................ 13
LIST OF FIGURES
Figure 1. Serial Port Timing............................................................................................................. 6 Figure 2. Typical Connection Diagram ............................................................................................ 7 Figure 3. Serial Port Data Transfer ................................................................................................. 8 Figure 4. Close-up of One Data Frame ........................................................................................... 9 Figure 5. Generating VA- with a Charge Pump............................................................................. 10
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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1. CHARACTERISTICS AND SPECIFICATIONS
ANALOG CHARACTERISTICS (TA = -40 C to +85 C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V; VA- = -2 V 10%; External VREF+ = 1.2 V; XIN = 4.000 MHz; AGND, DGND = 0.0V.)(See Notes 1 and 2)
Parameter Accuracy (All Channels) Total Harmonic Distortion Common Mode Rejection Common Mode + Signal on Input Input Sampling Rate Analog Inputs (Current Channels) Differential Input Voltage Range [ For example: (vIIN1+) - (vIIN1-) ] Bipolar Offset Crosstalk (Channel-to-Channel) Input Capacitance Effective Input Impedance Gain=20 Gain=1 Gain=20 Gain=1 (50, 60 Hz) Gain = 20 Gain = 1 (Note 3) Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 Gain=20 Gain=1 VIN Gain=1 (50, 60 Hz) IC (Note 3) EII VOS IC IC EII EII IIN VOS VOS 50 OWRS = "0" OWRS = "1" OWR OWR 40 800 0.500 10 500 800 20 3 XIN/2048 XIN/1024 1 20 -120 20 1 600 1 20 2.5 50 3.75 75 25 -120 0.2 4 20 50 75 mV mV mV mV dB pF pF k k
Vrms Vrms Vrms Vrms Vrms Vrms
Symbol THD (DC, 50, 60 Hz) CMRR
Min 74 80 VA-
Typ XIN/4
Max VA+ -
Unit dB dB V Hz
Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz Analog Inputs (Voltage Channels) Differential Input Voltage Range [ For example: (vVIN1+) - (vVIN1-) ] Bipolar Offset Crosstalk to any other channel at full-scale Input Capacitance Effective Input Impedance Noise (Referred to Input) 0-60 Hz 0-1 kHz 0-2 kHz Dynamic Characteristics High Rate Filter Output Word Rate
mV mV dB pF M Vrms Vrms Vrms Hz Hz
Notes: 1. Specifications guaranteed by design, characterization, and/or test. 2. Analog signals are relative to AGND and digital signals to DGND unless otherwise noted. 3. Effective Input Impedance (EII) varies with clock frequency (XIN) and Input Capacitance (IC) EII = 1/(IC*XIN/4)
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ANALOG CHARACTERISITCS (continued)
Parameter Reference Output Output Voltage Temperature Coefficient Load Regulation Power Supply Rejection Reference Input Input Voltage Range Input Capacitance Input CVF Current Power Supplies Power Supply Currents Power Consumption Power Supply Rejection (see Note 5) IA+ ID+ (Note 4) (DC) (50, 60 Hz) PSCA PSCD PC PSRR PSRR 50 60 3 4 27 mA mA mW dB dB VREF+ 1.15 1.2 1.25 10 1 V pF A (Output Current 1A Source or Sink) VR PSRR REFOUT 1.15 60 20 6 1.25 50 10 V ppm/C mV dB Symbol Min Typ Max Unit
Notes: 4. All outputs unloaded. All inputs CMOS level. 5. Definition for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 3V, AGND = DGND = 0V, VA- = -2V (using charge-pump circuit with CPD). In addition, a 106.07 mV rms (60 Hz) sinewave is imposed onto the VA+ and VD+ pins. The "+" and "-" input pins of both input channels are shorted to VA-. 2048 instantaneous digital output data words are collected for the channel under test. The rms value of the digital sinusoidal output signal is calculated, and this rms value is converted into the rms value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel's inputs, in order to cause the same digital sinusoidal output. This voltage is then defined as Veq. PSRR is then (in dB):
106.07 PSRR = 20 log --------------- V eq
DIGITAL CHARACTERISTICS (TA = -40 C to +85 C; +2.7V < VA+ < +3.5V; +2.7V < VD+ < +3.5V;
VA- = -2 V 10%; AGND, DGND = 0.0 V) (See Note 6) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage Low-Level Output Voltage Input Leakage Current 3-State Leakage Current Digital Output Pin Capacitance Notes: 6. All measurements performed under static conditions. 7. For OWRS and GAIN pins, input leakage current is 30 A (Max). Iout = -5.0 mA Iout = 5.0 mA (Note 7) Symbol VIH VIL VOH VOL Iin IOZ Cout Min 0.6 VD+ 0.0 (VD+) - 1.0 Typ 1 9 Max VD+ 0.8 0.4 10 10 Unit V V V V A A pF
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RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0.0 V)
Parameter DC Power Supplies Positive Digital Positive Analog Negative Analog Symbol VD+ VA+ VAVREF+ Min 2.7 2.7 -2.2 Typ 3.0 3.0 -2.0 1.2 Max 3.5 3.5 -1.8 Unit V V V V
Voltage Reference Input
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0.0 V; See Note 8.)
Parameter DC Power Supplies Positive Digital Positive Analog Negative Analog (Note 9 and 10) (Note 11) All Analog Pins All Digital Pins Symbol VD+ VA+ VAIIN IOUT PDN VINA VIND TA Tstg Min -0.3 -0.3 -2.5 VA- - 0.3 -0.3 -40 -65 Typ Max +3.5 +3.5 -0.3 10 25 500 (VA+) + 0.3 (VD+) + 0.3 85 150 Unit V V V mA mA mW V V C C
Input Current, Any Pin Except Supplies Output Current Power Dissipation Analog Input Voltage Digital Input Voltage Ambient Operating Temperature Storage Temperature
Notes: 8. All voltages with respect to AGND. 9. Applies to all pins including continuous over-voltage conditions at the analog input (AIN) pins. 10. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is 50 mA. 11. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
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SWITCHING CHARACTERISTICS (TA = -40 C to +85 C; VA+, VD+ = 3.0 V 10%; VA- = -2 V
10%; DGND = AGND = 0.0 V; Logic Levels: Logic 0 = 0.0 V, Logic 1 = VD+; CL = 50pF)) Parameter Master Clock Frequency Master Clock Duty Cycle Rise Times Fall Times Serial Port Timing Serial Clock Frequency (Note 12) OWRS = "0" OWRS = "1" Pulse Width High (Note 12) Pulse Width Low (Note 10) (Note 12) (Note 12) SCLK SCLK t1 t2 t3 t4 t5 t6 t7 500 1000 0.5 0.5 0.5 1 50 50 50 kHz kHz SCLK SCLK ns SCLK SCLK ns ns Any Digital Input (Note 13) Any Digital Output Any Digital Input (Note 13) Any Digital Output (Note 12) Symbol XIN trise tfall Min 3 40 Typ 4.000 50 50 Max 5 60 1.0 1.0 Unit MHz % s ns s ns
Serial Clock SCLK falling to New Data Bit
FSO Falling to SCLK Rising Delay FSO Pulse Width SE Rising to Output Enabled SE Falling to Output in Tri-state
Notes: 12. Device parameters are specified with a 4.000 MHz clock, OWRS = 1. 13. Specified using 10% and 90% points on wave-form of interest. Output loaded with 50 pF.
SDO
MSB(V1)
MSB(V1) - 1
LSB(I3)
t3 SCLK t4 FSO t5
t1
t2
t6 SE t6
Figure 1. Serial Port Timing
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2. GENERAL DESCRIPTION
The CS5451 is designed for 3-phase power meter applications and interfaces to a current transformers or shunt to measure current, and a resistive divider or transformer to measure voltage. The CS5451 combines six modulators and decimation filters, three channels assigned for current input that have programmable input gain amplifiers, and three channels assigned for voltage input. The CS5451 includes six decimation filters that output data at a 2000 Hz or 4000 Hz output word rate (OWR) when the input frequency at XIN = 4.096 MHz. The device outputs data on a serial output port.
2.1
Theory of Operation
The CS5451 is designed to operate from a single +3V supply and provides a 40 mV and 800 mV input range for the current channels and 800 mV range for the voltage channels. These voltages represent the maximum zero-to-peak voltage levels that can be presented to the inputs. The CS5451 is designed to accommodate common mode + signal levels from VA- to VA+. Figure 2 illustrates the CS5451 typical inputs and power supply connections.
+3 V
VA+ REFIN Optional External Reference REFOUT
VD+
1.2 V
V
+ PHASE
VIN1+, VIN2+, or VIN3+
VIN1-, VIN2-, or VIN3-
IIN1+, IIN2+, or IIN3+ I PHASE
NOTE: Current input channels actually measure voltage.
IIN1-, IIN2-, or IIN3-
AGND
VA-
DGND
-2 V
Figure 2. Typical Connection Diagram DS458PP4 7
CS5451
2.2 Performing Measurements 2.3 High Rate Digital Filters
The converter outputs are transferred in 16-bit signed (two's complement) data formats as a percentage of full scale. Table 1 below illustrates the ideal relationship between the differential voltage presented any one of the input channels and the corresponding output code. Note that for the current channels, the state of the GAIN input pin is assumed to driven low such that the PGA gain on the current channels is 1x. If the PGA gain of the current channels is set to 20x, a +40 mV differential voltage is presented across any pair of "IINk+" and "IINk-" pins (k = 1, 2, 3) would cause a (nominal) output code of 32767.
Differential Input Output Code Output Code Voltage (mV) (hexadecimal) (decimal) +800 0.0122 to 0.0366 -0.0122 to 0.0122 -0.0122 to -0.0366 -800 7FFF 0001 0000 FFFF 8000 32767 1 0 -1 -32768
If the OWRS pin is set to logic low, the high-rate filters are implemented as fixed sinc3 filters with the following transfer function:
1 - z - 256 3 H ( z ) = --------------------- -1 1-z
This filter samples the modulator bit stream at XIN/8 Hz and decimates to XIN/2048 Hz. If the OWRS pin is set to logic high, then the transfer function is
1 - z - 128 3 H ( z ) = --------------------- -1 1-z
The above filter samples the modulator bit stream at XIN/8 Hz and decimates to XIN/1024 Hz.
2.4
Serial Interface
Table 1. Nominal Relationship for Differential Input Voltage vs. Output Code, for all channels. (Assume PGA gain is set to 1x.)
The CS5451 communicates with a target device via a master serial data output port. Output data is provided on the SDO output synchronous with the SCLK output. A third output, FSO, is a framing signal used to signal the start of output data. These three outputs will be driven as long as the SE (serial
SCLK
96 SCLKs
FSO
Each data segment is 16 bits long.
SDO
Channel 1 V Channel 1 I Channel 2 V Channel 3 I Channel 3 V Channel 2 I
Figure 3. Serial Port Data Transfer
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96 SCLKs
SCLK
... ...
15 14 13 12 11 10 9 8 7 6 543 2 1 0 15 14 13 12 11 10 9 8 7654 3 2 1 0 15 14
... ...
... 3 2 1 0
FSO
SDO
[ Undefined ] Channel 1 ( V ) Channel 1 (I )
...
...
[ Undefined ]
Ch. 2 ( V )...Ch. 2 ( I )... Ch. 3 ( V )... Ch. 3 ( I )
Figure 4. Close-up of One Data Frame
enable) input is held high. Otherwise, these outputs will be high impedance. Data out (SDO) changes as a result of SCLK falling, and always outputs valid data with SCLK rising. When data is being transferred, the SCLK frequency is either 1/8 of the XIN input frequency (when OWRS is held low) or 1/4 of the XIN input frequency (when OWRS is held high). Any other time, SCLK is held low. (See Figures 3 and 4.) The framing signal (FSO) output is normally low, but produces a high level pulse lasting one SCLK period when the instantaneous voltage/current data samples are about to be transmitted out of the serial interface (after each A/D conversion cycle). Note: SCLK is not active during FSO high. For 96 SCLK periods after FSO falls, SCLK is active and SDO produces valid output. Six channels of 16 bit data are output, MSB first. Voltage and current measurements are output (in that order) for three phases. SCLK will then be held low until the next sample period.
2.6
Analog Inputs
The analog inputs of the CS5451 are bipolar voltage inputs: Three voltage channel inputs VIN(1-3) and three current channel inputs IIN(1-3). The CS5451 accommodates a full scale range of 40 mV or 800 mV on the Current Channels and 800 mV on the Voltage Channels.
2.7
Voltage Reference
The CS5451 is specified for operation with a +1.2 V reference between the VREFIN and AGND pins. The converter includes an internal 1.2 V reference (50 ppm/C drift) that can be used by connecting the VREFOUT pin to the VREFIN pin of the device. If higher accuracy/stability is required, an external reference can be used.
2.8
Power Supply
2.5
System Initialization
When power to the CS5451 is applied, the chip must be held in a reset condition using the RESET input. A hardware reset is initiated when the RESET pin is forced low with a minimum pulse width of 50 ns.
The low, stable analog power consumption and superior supply rejection of the CS5451 allow for the use of a simple charge-pump negative supply generator. The use of a negative supply alleviates the need for level shifting of the analog inputs. The CPD pin and capacitor C1 provide the necessary analog supply current as shown in Figure 5. The Schottky diodes D1 and D2 are chosen for their low forward voltages and high-speed capabilities. The capacitor C2 provides the required charge storage and bypassing of the negative supply. The CPD output signal provides the charge pump driver sig9
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CS5451
nal. The frequency of the charge pump driver signal is synchronous to XIN. The nominal average frequency is 1 Mhz. The level on the VA- pin is fed back internally so that the CPD output will regulate the VA- level to -2/3 of VA+ level. 12.5%. Therefore, the value of C1 should be reduced by 12.5%, making the new value for C1 to be 35 nF. For more information about the operation of this type of charge pump circuit, the reader can refer to Cirrus Logic, Inc.'s application note AN152: Using the CS5521/24/28, and CS5525/26 Charge Pump Drive for External Loads.
CPD
2.9
40 nF C1 D2 BAT 85 D1 BAT 85 AGND
PCB Layout
VA-
C2 1 F
For optimal performance, the CS5460A should be placed entirely over an analog ground plane with both the VA- and DGND pins of the device connected to the analog plane. Place the analog-digital plane split immediately adjacent to the digital portion of the chip.
Note: Refer to the CDB5460A Evaluation Board for suggested layout details and Applications Note 18 for more detailed layout guidelines. Before layout, please call for our Free Schematic Review Service.
Figure 5. Generating VA- with a Charge Pump
Note the value of C1 in Figure 5. The 40 nF value is recommended when the input frequency presented to the XIN pin is 4.00 MHz. If the user decides to use an XIN frequency that is significantly different than 4.00 MHz (if the XIN frequency is increased/decreased by more than 5% of 4.00 MHz, then it is recommended that the user should alter the value of C1. The percentage change in the value of C1 (with respect to a reference value of 40 nF) should be inversely proportional to the percentage change in the XIN frequency. For example, if the XIN frequency is increased from 4.00 MHz to 4.5 MHz, this represents a percentage increase of
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3. PIN DESCRIPTION
Serial Clock Output SCLK Serial Data Output SDO Frame Sync FSO Serial Port Enable SE Current Input Gain GAIN Analog Ground AGND Reference Input VREFIN Reference Output VREFOUT Positive Analog Supply VA+ Negative Analog Supply VADifferential Voltage Input 3 VIN3+ Differential Voltage Input 3 VIN3Differential Current Input 3 IIN3+ Differential Current Input 3 IIN31 2 3 4 5 6 7
8
28
27 26
25 24 23 22 21 20 19
18
9 10 11 12 13 14
17 16 15
VD+ DGND CPD XIN RESET OWRS VIN1+ VIN1IIN1+ IIN1VIN2+ VIN2IIN2+ IIN2-
Digital Supply Digital Ground Charge Pump Drive Master Clock Reset Output Word Rate Select Differential Voltage Input 1 Differential Voltage Input 1 Differential Current Input 1 Differential Current Input 1 Differential Voltage Input 2 Differential Voltage Input 2 Differential Current Input 2 Differential Current Input 2
Clock Generator XIN - Master Clock Input Control Pins and Serial Data I/O SE - Serial Port Enable
When SE is low, the output pins of the serial port are 3-stated.
SDO - Serial Port Output
Data will be at a rate determined by SCLK.
FSO - Frame Signal Output
Framing signal output for data transfer from SDO pin.
SCLK - Serial Clock Output
A clock signal on this pin determines the output rate of data for SDO pin. Rate of SCLK is determined by XIN frequency and state of OWRS input pin.
RESET - Reset
When reset is taken low, all internal registers are set to their default states.
GAIN - Input Gain Control
Sets input gain for current channels. A logic high sets internal gain to 1, a logic low level sets the gain to 20. If no connection is made to this pin, it will default to logic low level (through internal 200K resistor to DGND).
OWRS - Output Word Rate Select
When OWRS is set to logic low, the output word rate (OWR) at SDO pin is XIN/2048 (Hz). When set to logic high, the OWR at SDO pin is XIN/1024 (Hz). If no connection is made to this pin, then OWRS will default to logic low level (through internal 200K resistor to DGND).
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CS5451
Measurement and Reference Input IIN(1-3)+, IIN(1-3)- - Differential Current Inputs
Differential analog input pins for current channels.
VIN(1-3)+, VIN(1-3)- - Differential Voltage Inputs
Differential analog input pins for voltage channels.
VREFOUT - Voltage Reference Output
The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 1.2 V and is referenced to the AGND pin on the converter.
VREFIN - Voltage Reference Input
The voltage input to this pin establishes the voltage reference for the on-chip modulator.
Power Supply Connections VA+ - Positive Analog Supply
The positive analog supply is nominally +3 V 10% relative to AGND.
VA- - Negative Analog Supply
The negative analog supply is nominally -2 V 10% relative to AGND.
AGND - Analog Ground
The analog ground pin for input signals.
VD+ - Positive Digital Supply
The positive digital supply is nominally +3 V 10% relative to DGND.
DGND - Digital Ground
The digital ground is typically at the same level as AGND.
CPD - Charge Pump Drive
This output pin drives the external charge pump circuitry to create a negative supply voltage.
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4. PACKAGE DIMENSIONS
28L SSOP PACKAGE DRAWING
N
D
E11 A2 A1 A
E
L
e
b2 SIDE VIEW
END VIEW
SEATING PLANE
123
TOP VIEW
INCHES DIM A A1 A2 b D E E1 e L MIN -0.002 0.064 0.009 0.390 0.291 0.197 0.022 0.025 0 NOM -0.006 0.069 -0.4015 0.307 0.209 0.026 0.0354 4 MAX 0.084 0.010 0.074 0.015 0.413 0.323 0.220 0.030 0.041 8 MIN -0.05 1.62 0.22 9.90 7.40 5.00 0.55 0.63 0
MILLIMETERS NOM -0.13 1.75 -10.20 7.80 5.30 0.65 0.90 4 MAX 2.13 0.25 1.88 0.38 10.50 8.20 5.60 0.75 1.03 8
NOTE
2,3 1 1
JEDEC #: MO-150 Notes: 1. "D" and "E1" are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension "b" does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of "b" dimension at maximum material condition. Dambar intrusion shall not reduce dimension "b" by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips.
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